A very large cache (EDRAM or embedded DRAM (dynamic random access memory)) can be implemented as a sector cache to reduce the size of a tag used to access cache lines. With a sector size of 1K-byte block (known as a ‘superline’) that contains 16 consecutive 64-byte cache lines, the tag size can be reduced by a factor of 16 compared to a non-sectored design. Line state of each cache line also needs to be in the tag. Thus, to further reduce storage size in the tag array, instead of having a line state error correction code(s) (ECC) generated for each individual cache line, all cache line states in a superline can be combined into a 32-bit line state vector with one ECC, thereby reducing total ECC bits for line states in a superline from 4×16=64 bits to 7 bits.
With combined line state, line state update becomes rather complex. Line state ECC needs to be recalculated whenever line state in one of 16 cache lines in a superline changes. The line state update requires a read-modify-write (RMW) operation to merge the new line state into line state vector and recalculate its ECC. Performing RMW requires high power logic and is not possible to be done in the tag array with small signal array (SSA) design. In addition, the line state update should be serialized to ensure new state and ECC correctly pass from previous update to the next.